Verilink 1558A (CG) Configuration/Installation Guide Bedienungsanleitung PDF herunterladen (Seite 2)

1558A Block Diagram

NET

-20 to 56 VDC/RTN

(Power A)

-20 to 56 VDC/RTN

(Power B)

Power

COM Bus

DTE

RJ48

Supply

±12 VDC

+5 VDC

Power

Line

Deframer

NET A

Framer

Loop

Line

Protection

Fac.

Loop

PLB

APS

Select

Path A/B

Bridge

Jack

Receive

Jack

NET A

Bridge

Jack

Transmit

Jack

RJ48

Line

Protection

NET

Line

Deframer

NET B

Framer

Loop

Line

Protection

Fac.

Loop

PLB

Bridge

Jack

Receive

Jack

NET B

Bridge

Jack

Transmit

Jack

RJ48

Line

Protection

Framer

Deframer

Eq.

Loop

Line

Protection

Line

Protection

Bridge

Jack

Receive

Jack

Bridge

Jack

Transmit

Jack

DTE

Bypass Mode

(Path A to DTE)

Fault

CPU

Fault

Signal

Split

ROM

RAM

CPU

Loop

Set/Reset

SUPV

Port

Performance History,

Alarms, Unit Address

OUT

COM Bus

Alarm

Contacts

(COM,

NO, NC)

BERT: QRSS,

1:8, 3:24, etc.

NET B

NET A

Switch S4 Switch S3

12345678

128

NOTE

: Address values are additive for all switch positions

set to the ‘ON’ position. For example, if positions 1 and 3 are

set to the ‘ON’ position, the unit address is set to 5 (1+4).

Also note that Switch 3, Position 1 is factory wired to the ON

position. This forces all Path A unit addresses to odd values

and all Path B addresses to even values. The factory default

is all switches set to ‘OFF’ (Path A address set to the ONE

and Path B address set to Two)

Va l u e

Off

12345678

Path A LBO

Path B LBO

DTE DSX

Not Used

LBO S4-1 S4-2 S4-3 S4-4

0 dB Off

Off Off Off

7.5 dB Off On Off On

15 dB On Off On Off

22.5 dB On On On On

S4-5 S4-6 S4-7 DSX

Off

Off Off 133 ft

Off Off On 266 ft

Off On Off 399 ft

Off On On 533 ft

On Off Off 655 ft

Off

1 2

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